The Indigo2 provides an easy upgrade path for newer and faster CPUs; the CPU and the second- level cache is mounted on an easily changed CPU module which can be swapped without changing the rest of the system board.
The Indigo2 system board's main memory capacity is a full 384 MB of DRAM. Because the system board replaces SIMM-mounted DRAM interleave controllers with motherboard mounted DMUX chips, main memory is implemented with standard 36-bit-wide DRAM SIMMs.
The block diagram illustrated in Figure 2 illustrates the Indigo2 system board.
The system board contains four functional sections, as illustrated in Figure 2:
3.1.1 MIPS R4400SC CPU Module
System performance estimates of the 200 MHz R4400SC exceed 180 MIPS (Dhrystone 1.1), 34 MFLOPS (double precision), 124 SPECfp92, and 116 SPECint92.
At the fast R4400SC CPU clock rate, some instruction steps such as cache reads and writes can't execute in a single pipelined cycle. Superpipelining executes each of these critically slow steps in a single cycle to provide higher throughput. To do so, it first breaks instruction steps into substeps. The substeps are then pipelined in a process separate from standard pipelining, which executes the full step in a single cycle. R4400SC superpipelining is optimized so that it requires little control logic and instruction structure.
The R4400SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.
System performance estimates of the 133 MHz R4600 exceed 169 MIPS (Dhrystone I.I), 20 MFLOPS (double precision), 72 SPECfp92, and 109 SPECint92.
The internal pipeline of the R4600 operates at twice the frequency of the input clock. The CPU achieves high throughput by pipelining cache accesses, using virtual-indexed primary caches, and allowing the latency of certain functional units to span more than the internal clock cycle.
The R4600SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.
The DMUX ASICs are a two-chip slice of a data crossbar between the CPU, main memory, and the GIO64 bus. The two DMUX chips are, together, a data path with control signals generated by the MC. They isolate the CPU bus from the memory system and the GIO64 bus. They also contain synchronization FIFOs to perform flow control between the various subsystems, and they interleave main memory to increase peak memory bandwidth.
The INT2 ASIC is connected to the MC chip instead of directly to the CPU. The MC chip passes on all interrupts from INT2 to the CPU.
The GIO64 is the Indigo2 workstation's main system bus and is designed for very high speed data transfer. It connects the Indigo main systems: the processor core, main memory, the I/O systems, the graphics system, and any boards plugged into the GIO64 expansion slots. It is a synchronous, multiplexed address/data, burst mode bus that is clocked independently of the CPU.
EISA Bus Controller
The HPC3 ASIC, the High Performance Peripheral Controller, is a custom Silicon Graphics chip that connects to the GIO64 bus and directly to several of the I/O ports. It is the heart of the I/O system, and quickly transfers data between main memory and a rich collection of peripheral devices, at the peak rates of such devices. It uses minimum bandwidth on the GIO64 bus, freeing the bus for other data transfers.
The HPC3 permits fast data interchange between peripheral devices and main memory without involving the CPU, improving both CPU and peripheral performance. For each peripheral device, the HPC3 provides an independent FIFO data buffer, and supports DMA to main memory through the GIO64 bus and the MC ASIC. It provides interfaces to the serial ports and other devices through the peripheral bus.
The Ethernet interface consists of both an AUI and a 10BASE-T Ethernet port supported by a controller that is connected directly to the HPC3 ASIC. The interface automatically selects between the AUI and 10Base-T ports; the user does not have to manually change a DIP switch. The HPC3 supplies the logic required to retransmit packets when collisions occur and to manage the interface's 64-byte FIFO buffer. When the HPC3 receives a packet, it interrupts the CPU after it writes the packet into memory. When transmitting, it interrupts the CPU when a packet is successfully sent or when 16 transmission attempts have all failed.
The Fast SCSI-2 interface consists of one internal channel and one external channel. The internal channel connects three internal SCSI devices. The external channel provides an external high-density SCSI port on the rear of the central unit. Each Fast SCSI-2 channel is supported by a SCSI controller connected directly to the HPC3 ASIC. The HPC3 uses two FIFO buffers to enable hurst use of the GIO bus.
The parallel port interface provides a bidirectional Centronics parallel port to connect printers, plotters, scanners, and other similar devices. The port is connected to the peripheral bus and provides a FIFO buffer used to transfer data between main memory and the parallel port at up to 1.0 MB/sec.
The peripheral bus (P-Bus) is a 20-bit address, 16-bit data bus used by the HPC3 for additional peripheral support. It connects the boot PROMs, a real-time clock, the timer, two serial ports, a mouse port, a keyboard port, the EPPI ASIC parallel port interface and the audio system through the HAL2 ASIC. There is a 384 byte memory that is shared by all of the peripheral bus devices to buffer DMA transfers to and from memory.
The serial interface consists of two serial ports, controlled by a DUART chip that connects to the Peripheral Bus. They can be configured as EIA-232 standard devices or as external Apple Macintosh compatible connectors that can connect to common Macintosh peripherals such as laser printers and scanners. The serial ports support a transfer rate of up to 38.4 KBaud.
The PS/2 standard keyboard and mouse are controlled by industry-standard hardware and firmware, ensuring compatibility with a wide variety of third party input devices.
The HAL2 chip is a 1 micron, 28k gate CMOS gate array which contains the data path and control logic to interface the HPC3 peripheral bus and the audio devices on the module. The major functional blocks connected to the HAL2 are the two CS4216 CODECS, the CS8401 AES transmitter, the CS8411 AES receiver, the headphone and speaker gain circuit, the microphone input circuit, and the four-channel mode output switch.
Notable features of the HAL2 design include:
In the normal mode of operation, the Codec A DAC is used for analog output and the Codec B ADC is used for analog input. The Codecs can use independent sample-rate clock generators from the HAL2, so that the analog input sample rate and the analog output sample rate may be selected independently. The analog input (to Codec B) is selectable from either the line or microphone inputs under software control. The analog output signal (from Codec A) is routed both to line-out and to the stereo headphone/internal loudspeaker circuit. The user gets true line-level signal and a volume-adjusted headphone/loudspeaker output.
The Indigo2 audio system provides an enhanced mode of operation that extends the number of simultaneously active analog input channels from 2 to 4 and the number of simultaneously active analog output channels from 2 to 4.
In 4-channel mode, both Codecs are synchronized to the same sample rate and the Codecs are used simultaneously for input (ADC) and output (DAC). Codec A's input (ADC) comes from the microphone input, Codec B's input (ADC) from the line input. Codec A's output continues to be routed to the line output, but Codec B's output is routed at line-levels to the headphone jack.
The Indigo2 microphone input circuit provides DC power for active circuitry in microphones that require it, while retaining compatibility with other types of microphones. Powered microphones, such as the one supplied with Indigo2, use this DC power to drive a large low-impedance signal back to the audio circuitry, avoiding the problems commonly associated with low-level microphone signals and electrically noisy computer environments.
The microphone input circuit accepts both monaural and stereo microphones. In addition to the input source switching and software-controlled gain functions available in the Codecs, the DC power feature and a hardware 20 dB gain stage may be enabled and disabled via software control.