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Indigo2 and POWER Indigo2 Technical Report

Section 3: IRIS Indigo2 CPU Boards

Indigo2 is available with the R4400 or R4600 CPU Module. The POWER Indigo2 is equipped with the R8000 CPU module. The Indigo2 system provides:

3.1 Processor Core

The processor core is centered around the CPU module, which contains the CPU and its secondary cache. The processor core uses three types of custom chips: the MC ASIC to give the CPU access to memory and the GIO64 bus; DMUX ASICs to isolate the CPU bus from the GIO64 bus; and the INT2 ASIC to deliver CPU interrupts.

3.1.1 MIPS R4400SC CPU Module

This MIPS R4400SC CPU (shown in Figure 3) contains the main processor, a floating point processor, a 16 KB onboard instruction cache, and an 16 KB onboard data cache. The R4400SC CPU also provides a dedicated interface to a 1 MB second-level cache. The 200 MHz R4400SC chip's external clock rate is 100 MHz, but it runs internally at 200 MHz. The 64-bit data and instruction paths to the chip's caches bring in data and instructions at a speed which minimizes cache misses and CPU idling.

System performance estimates of the 200 MHz R4400SC exceed 180 MIPS (Dhrystone 1.1), 34 MFLOPS (double precision), 124 SPECfp92, and 116 SPECint92.

[R4400 Block Diagram]

FIGURE 3 The functional sections of the MIPS R4400SC CPU.

The R4400SC uses superpipelining to achieve the fast internal speed. In normal pipelining, the CPU breaks each instruction into separate one-cycle steps (usually fetch, read, execute, memory, and write back), and then executes instructions at one-cycle intervals.

At the fast R4400SC CPU clock rate, some instruction steps such as cache reads and writes can't execute in a single pipelined cycle. Superpipelining executes each of these critically slow steps in a single cycle to provide higher throughput. To do so, it first breaks instruction steps into substeps. The substeps are then pipelined in a process separate from standard pipelining, which executes the full step in a single cycle. R4400SC superpipelining is optimized so that it requires little control logic and instruction structure.

The R4400SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.

3.1.2 MIPS R4600SC CPU Module

This MIPS R44600 CPU (shown in Figure 3) contains the main processor, a floating point processor, a 16 KB onboard instruction cache, and an 16 KB onboard data cache. The R4600 CPU also provides a dedicated interface to a 1 MB second-level cache. The R4600 chip's external clock rate is 66.67 MHz, hut it runs internally at 133 MHz. The 64-bit data and instruction paths to the chip's caches bring in data and instructions at a speed which minimizes cache misses and CPU idling.

System performance estimates of the 133 MHz R4600 exceed 169 MIPS (Dhrystone I.I), 20 MFLOPS (double precision), 72 SPECfp92, and 109 SPECint92.

[R4600 Block Diagram]

FIGURE 4 The functional sections of the MIPS R4600 CPU.

The R4600 uses a 5-stage pipeline similar to the R3000. This pipeline is simpler than the 8-stage superpipeline used in the R4400 and is more efficient (fewer pipeline stalls) in terms of branch and load latency.

The internal pipeline of the R4600 operates at twice the frequency of the input clock. The CPU achieves high throughput by pipelining cache accesses, using virtual-indexed primary caches, and allowing the latency of certain functional units to span more than the internal clock cycle.

The R4600SC CPU supports the MIPS 1 instruction set (used by the R3000A CPU), the MIPS 2 instruction set and the MIPS 3 instruction set. Data pathways in MIPS 3 are 64 bits wide, giving the system the ability to load and store full floating point double words in a single machine cycle. The MIPS 3 instruction set also contains synchronization and advanced cache control primitives.

3.1.3 MIPS R8000 Module

For information on the R8000 CPU, see Section 7 "The R8000 POWER Indigo2."

3.1.4 MC ASIC

The MC ASIC, the Memory Controller (shown in Figure 9), is a custom Silicon Graphics chip connected to the CPU module by the CPU bus. It's also connected to the GIO64 bus (the system bus), and has address and control lines connected to main memory. It performs many functions:

  • It provides an interface between main memory and the CPU core

  • It serves as a DMA (Direct Memory Access) controller for all memory requests from the graphics system or any other devices on the GIO64 bus

  • It acts as a system arbiter for the GIO64 bus

  • It provides single-word accesses for the CPU to GIO64 bus devices and to the graphics system

  • It passes on interrupts from the INT2 ASIC to the CPU

  • It initializes the CPU on powerup, executes CPU requests, refreshes memory, and checks data parity in memory

[MC ASIC Block Diagram]

FIGURE 5 A block diagram of the MC ASIC. The MC runs the system bus, handles memory access for CPU and GIO64 devices, works as a DMA controller, and fulfills other miscellaneous functions.

Of special note is the MC's ability to support Virtual DMA requests from processes running on the CPU. The process can also set up a DMA descriptor in MC and then request the DMA engine to start. The memory addresses used in the DMA descriptor are virtual memory addresses which the MC translates (using a TLB and UNIX page tables) to physical memory addresses. When the DMA operation is finished, an interrupt may be generated (if the interrupt is enabled in MC) to inform the CPU.

The DMUX ASICs are a two-chip slice of a data crossbar between the CPU, main memory, and the GIO64 bus. The two DMUX chips are, together, a data path with control signals generated by the MC. They isolate the CPU bus from the memory system and the GIO64 bus. They also contain synchronization FIFOs to perform flow control between the various subsystems, and they interleave main memory to increase peak memory bandwidth.

The INT2 ASIC is connected to the MC chip instead of directly to the CPU. The MC chip passes on all interrupts from INT2 to the CPU.

3.2 GIO64Bus

The GIO64 bus, the main system bus, provides a 64-bit wide data path.

The GIO64 is the Indigo2 workstation's main system bus and is designed for very high speed data transfer. It connects the Indigo main systems: the processor core, main memory, the I/O systems, the graphics system, and any boards plugged into the GIO64 expansion slots. It is a synchronous, multiplexed address/data, burst mode bus that is clocked independently of the CPU.

3.3 EISA Bus

The EISA subsystem consists of the EISA Interface Unit (EIU), a custom Silicon Graphics ASIC, and the Intel 82350DT EISA chip set. The EIU provides an interface for the high performance GIO64 bus and the Intel EISA chip set. The EIU performs the following:

The EIU is capable of burst transfers at the following data rates:

The Intel 82350DT chip set consists of an EISA Bus Controller (EBC), Integrated System Peripheral (ISP), and two EISA Bus Buffers (EBB). The 82350DT chip set performs the following:

EISA Bus Controller

Integrated System Peripheral

EISA Bus Buffers

3.4 Main Memory

Main memory, which is controlled by the two DMUX ASICs, provides system access to large amounts of DRAM. Memory consists of standard off-the-shelf 36-bit wide DRAM SIMMs (which must have 80 ns RAS access time and fast page-mode capability). To support the increased bandwidth of the R4400SC/R8000 CPU, the DMUX chips interleave the SIMMs to create a 64-bit wide two-way interleaved memory system.

[Memory Bank/Interleaving Diagram]

FIGURE 6 Memory on the R4400SC/R8000 CPU board interleaves SIMM strips in banks of four, and connects them to the CPU and the GIO64 bus with DMUX and MC chips.

Main memory can he configured to he as little as 32 megabytes or as much as 640 megabytes. The R4400SC/R8000 CPU board has 12 SIMM sockets, arranged in three groups of four. Each socket group must use SIMMs of the same size, but SIMM sizes can differ between groups to allow different memory configurations. Maximum capacity is:

3.5 The I/O System

The I/O system ties together a variety of I/O ports and the chips that drive them, a system clock, and the system PROM for booting up. It uses a peripheral bus to transfer some I/O data, and also uses a custom chip - the HPC3 ASIC - to provide an interface between the system and the GIO64 bus.

The HPC3 ASIC, the High Performance Peripheral Controller, is a custom Silicon Graphics chip that connects to the GIO64 bus and directly to several of the I/O ports. It is the heart of the I/O system, and quickly transfers data between main memory and a rich collection of peripheral devices, at the peak rates of such devices. It uses minimum bandwidth on the GIO64 bus, freeing the bus for other data transfers.

The HPC3 permits fast data interchange between peripheral devices and main memory without involving the CPU, improving both CPU and peripheral performance. For each peripheral device, the HPC3 provides an independent FIFO data buffer, and supports DMA to main memory through the GIO64 bus and the MC ASIC. It provides interfaces to the serial ports and other devices through the peripheral bus.

The Ethernet interface consists of both an AUI and a 10BASE-T Ethernet port supported by a controller that is connected directly to the HPC3 ASIC. The interface automatically selects between the AUI and 10Base-T ports; the user does not have to manually change a DIP switch. The HPC3 supplies the logic required to retransmit packets when collisions occur and to manage the interface's 64-byte FIFO buffer. When the HPC3 receives a packet, it interrupts the CPU after it writes the packet into memory. When transmitting, it interrupts the CPU when a packet is successfully sent or when 16 transmission attempts have all failed.

The Fast SCSI-2 interface consists of one internal channel and one external channel. The internal channel connects three internal SCSI devices. The external channel provides an external high-density SCSI port on the rear of the central unit. Each Fast SCSI-2 channel is supported by a SCSI controller connected directly to the HPC3 ASIC. The HPC3 uses two FIFO buffers to enable hurst use of the GIO bus.

The parallel port interface provides a bidirectional Centronics parallel port to connect printers, plotters, scanners, and other similar devices. The port is connected to the peripheral bus and provides a FIFO buffer used to transfer data between main memory and the parallel port at up to 1.0 MB/sec.

The peripheral bus (P-Bus) is a 20-bit address, 16-bit data bus used by the HPC3 for additional peripheral support. It connects the boot PROMs, a real-time clock, the timer, two serial ports, a mouse port, a keyboard port, the EPPI ASIC parallel port interface and the audio system through the HAL2 ASIC. There is a 384 byte memory that is shared by all of the peripheral bus devices to buffer DMA transfers to and from memory.

The serial interface consists of two serial ports, controlled by a DUART chip that connects to the Peripheral Bus. They can be configured as EIA-232 standard devices or as external Apple Macintosh compatible connectors that can connect to common Macintosh peripherals such as laser printers and scanners. The serial ports support a transfer rate of up to 38.4 KBaud.

The PS/2 standard keyboard and mouse are controlled by industry-standard hardware and firmware, ensuring compatibility with a wide variety of third party input devices.

3.6 The Audio System

The Indigo audio system shown in Figure 7 is a daughterboard that allows the Indigo2 to record, process, synthesize and play professional quality signals. The HAL2, a high density ASIC on the audio module, performs the I/O functions replacing the need for a dedicated digital signal processor. The new architecture provides more features, better real-time performance, much higher aggregate data rates, and lower cost, yet retains binary compatibility for application programs through the use of Silicon Graphics Audio Library (AL).

[Indigo2 Audio Block Diagram]
FIGURE 7 Indigo2 Audio Block Diagram

The Indigo2 audio system supports the standard Indigo workstation audio features:

The Indigo2 audio system also introduces several new features:

3.6.1 HAL2 ASIC

The Indigo2 audio system is built around a central controller chip, the HAL2 ASIC, two audio CODEC chips, an AES transmitter chip, an AES receiver chip, a microphone input circuit, a headphone/speaker amplifier circuit, and a four-channel-mode output switch.

The HAL2 chip is a 1 micron, 28k gate CMOS gate array which contains the data path and control logic to interface the HPC3 peripheral bus and the audio devices on the module. The major functional blocks connected to the HAL2 are the two CS4216 CODECS, the CS8401 AES transmitter, the CS8411 AES receiver, the headphone and speaker gain circuit, the microphone input circuit, and the four-channel mode output switch.

Notable features of the HAL2 design include:

  • Three independent clock generators

    • AES out

    • analog in

    • analog out

  • Each of the clock generators can select from three different timebases

  • The clock generators use Bresenham's algorithm to scale the input clocks by rational fractions

  • The time stamping clock is generated from the same timebase as the unix utime

  • Each audio device has its own DMA channel and clock generator

  • The DMA channel allocation is configurable in software

  • The audio devices attach with conventional 3-wire serial interfaces

  • In 4 channel mode, data from all four channels goes over the same DMA channel guaranteeing synchronization

3.6.2 Codecs

The Indigo2 audio system uses a pair of Crystal Semiconductor CS4216 stereo audio Codecs. These chips are highly integrated monolithic CMOS mixed-signal devices which make use of the latest signal conversion technology. Both the analog-to-digital converters (ADC) and digital-to- analog converters (DAC) are 64x-oversampling delta-sigma 16-bit converters. They also contain on-chip reconstruction and anti-aliasing filters, programmable input gain, and programmable input source switching. The filters' responses track the sampling rate, a significant advantage over the older fixed-response low-pass analog filter designs.

In the normal mode of operation, the Codec A DAC is used for analog output and the Codec B ADC is used for analog input. The Codecs can use independent sample-rate clock generators from the HAL2, so that the analog input sample rate and the analog output sample rate may be selected independently. The analog input (to Codec B) is selectable from either the line or microphone inputs under software control. The analog output signal (from Codec A) is routed both to line-out and to the stereo headphone/internal loudspeaker circuit. The user gets true line-level signal and a volume-adjusted headphone/loudspeaker output.

The Indigo2 audio system provides an enhanced mode of operation that extends the number of simultaneously active analog input channels from 2 to 4 and the number of simultaneously active analog output channels from 2 to 4.

In 4-channel mode, both Codecs are synchronized to the same sample rate and the Codecs are used simultaneously for input (ADC) and output (DAC). Codec A's input (ADC) comes from the microphone input, Codec B's input (ADC) from the line input. Codec A's output continues to be routed to the line output, but Codec B's output is routed at line-levels to the headphone jack.

3.6.3 Serial Digital Audio Transmitter

The Indigo2 has an industry-standard, transformer-coupled, serial digital audio output that supports up to 24-bit stereo samples at all available sample clock rates. The audio and non-audio bits may be coded to support both professional and consumer standards (AES3, IEC958).

3.6.4 Serial Digital Audio Receiver

The Indigo has an industry-standard, transformer, coupled, serial digital audio input that supp up to 24-bit stereo samples at up to a 50 kHz sample rate. The sample rate clock recovered ft this input may he used to generate synchronized sample clocks for the Codecs and serial digi audio transmitter. All of the hits received in the serial digital channel including U, C, V. and P input to the computer. Both professional and consumer coding formats are supported by AES3, IEC958.

3.6.5 Microphone

The Indigo2 comes standard with a high-quality, electret condenser monaural lapel microphone. The microphone is omnidirectional and has both a wide-frequency response and a large dynamic range.

The Indigo2 microphone input circuit provides DC power for active circuitry in microphones that require it, while retaining compatibility with other types of microphones. Powered microphones, such as the one supplied with Indigo2, use this DC power to drive a large low-impedance signal back to the audio circuitry, avoiding the problems commonly associated with low-level microphone signals and electrically noisy computer environments.

The microphone input circuit accepts both monaural and stereo microphones. In addition to the input source switching and software-controlled gain functions available in the Codecs, the DC power feature and a hardware 20 dB gain stage may be enabled and disabled via software control.

3.6.6 Internal Speaker

The internal speaker in the Indigo2 audio system outputs the sum of the left and right line-out channels. The speaker is shielded to protect the graphics and video monitors from the speaker's magnetic field. Speaker volume is software controlled.

3.6.7 Headphone Output

The Indigo2 audio system provides a stereo headphone output connection, suitable for connecting standard headphones without need for external amplifiers. The headphone volume for each channel is software controlled. When a headphone is plugged into the connector, the internal speaker is automatically disconnected.

3.7 Expansion Slots

The Indigo2 has four expansion slots; all four slots have EISA bus connectors, three of the slo have GIO64 pipelined bus connectors as well. The EISA bus fully conforms to version 3.12 of EISA standard, allowing the use of a large variety of EISA and ISA components.

Ian's SGI Depot: FOR SALE! SGI Systems, Parts, Spares and Upgrades

(check my current auctions!)
[WhatsNew] [P.I.] [Indigo] [Indy] [O2] [Indigo2] [Crimson] [Challenge] [Onyx] [Octane] [Origin] [Onyx2]
[Future Technology Research Index] [SGI Tech/Advice Index] [Nintendo64 Tech Info Index]