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Indigo2 and POWER Indigo2 Technical Report

Section 4: XL Graphics

XL Graphics is the Indigo2 entry graphics subsystem. It is available only on the R4400SC version of Indigo2; it is not available with the R8000 configuration.

XL Graphics uses the CPU to implement the IRIS Graphics Library application programming interface rather than having a dedicated Geometry Engine. XL Graphics, shown in block diagram in Figure 8, provides high resolution, full 24-bit color and includes the following:

[XL Block Diagram]

FIGURE 8: The XL Graphics Board. The shaded boxes show Silicon Graphics-designed ASICs.

The main bus on the XL Graphics board provides a communication path between the elements of the graphics subsystem. The XL Graphics board is connected to the GIO64 bus via the REX3 ASIC, which can access data from the CPU at a burst rate of 267 MBytes per second.

4.1 Graphics Processing

XL Graphics makes extensive use of the power of the R4400 CPU by implementing the IRIS Graphics Library application programming interface as a set of highly efficient software algorithms. Because of the flexibility inherent in the software-based IRIS GL implementation, new graphics functions can be added as new software releases, without the need for costly hardware upgrades.

The CPU uses the IRIS GL to transform three-dimensional polygons to 2D screen coordinates, decompose them into triangles, and finally decompose the triangles into spans by exact point sampling of the triangle's interior. These spans are then passed on to the REX3 ASIC, which interpolates them and renders the results into the framebuffer.

Figure 9 shows how 3D polygons are processed by the CPU and the REX3 ASIC. All transformation, clipping, and lighting calculations for points, lines, and polygons are performed in software by the CPU, including Z-buffer calculations, which are implemented in 32-bit resolution without the use of dedicated Z-buffer bitplanes.

[XL Graphics Processing]

FIGURE 9 XL Graphics processing. The majority of XL Graphics computation is performed in software by the CPU.

XL Graphics offers several advantages in speed and flexibility over hardware-based graphics systems:

4.2 The Raster Engine

The Raster Engine (REX3) is a pipelined, pixel-filling, and line-drawing ASIC which provides pixel shade, pattern, logicop, and blend operations for point, span, block, and integer or subpixel positioned line addressing modes. The REX3 ASIC achieves outstanding performance by the following techniques:

The REX3 has five basic drawing primitives: point, line, span, block, and screen-to-screen copy. Draw commands can modify either pixel, overlay, or CID planes. The REX3 hardware recognizes a total X11 pixel address space of 64K x 64K pixels or a GL pixel address space of 4096 x 4096 pixels including 64 x 1K pixels of offscreen memory. REX3 can read pixel, overlay, pop-up, or CID information from both onscreen and offscreen memory.

REX3 supports both flat and linear (Gouraud) shading in both color index and RGB formats with optional dithering. The peak fill rates for the REX3 are:

Dithering is window-relative in REX3, in contrast to the screen-relative dithering supplied in other GL implementations. This has the benefit of allowing a window to be moved while it is rendering, without creating artifacts. REX3 also includes the following features:

In addition to features that support windowing, REX3 also has features to support IRIS GL and X11 library functions. These include:

4.3 Framebuffer and Clipping Planes

There are four kinds of bitplanes in the XL Graphics subsystem: pixel, pop-ups, overlay, and clipping ID (CID) planes. The four bitplanes are implemented as a framebuffer in a 12x256Kx16 bank of VRAM.

Pixel planes hold 24 bits of information for each pixel of the display. In single buffer mode, the framebuffer contains a 12-bit color index or 24-bit RGB (8 bits each for red, green, and blue).

Pop-up planes, holding 2 bits per pixel, are used for pop-up menus, dialog boxes, and other components of a graphical user interface that temporarily obscure the image.

Clipping ID planes, also holding 2 bits per pixel, store information about which parts of windows are visible on the display. Multiple windows can overlap each other, totally or partially obscuring their contents. Individual pixels can be masked against a window boundary, thereby supporting non-rectangular windows without imposing additional overhead on the window system. The clipping ID (CID) planes are in the framebuffer VRAM.

The overlay planes on XL Graphics hold 8 bits per pixel.

The framebuffer is connected to the REX3 ASIC via the RB2s. Full use of the VRAM bandwidth is realized through a 128 pixel wide data path that connects the framebuffer to the RB2 ASIC. The framebuffer displays to a 1024 x 768 or 1280 x 1024 pixel monitor.

4.4 Color Lookup

The display of pixel data is controlled by the VC2 ASIC. It determines the timing of transfer cycles performed by the RFX3. The serial VRAM data is buffered in the RO1 ASICs and then sent at half video rate to a pair of XMAP9 ASICs. The XMAP9 ASICs format the lookup index on a per-window basis as instructed by the VC2 for both color index and RGB modes, double-buffering, pixel depths, a pop-up cursor, and overlay planes.

Depending on the mode, each pixel to be displayed is formatted with an offset of n x 256 in order to index the desired section of the CMAP RAM as shown in Figure 10. This resulting lookup index is passed to the CMAP ASICs which generate 24-bit RGB values for display. These values finally enter the RAMDAC where they are gamma-corrected for the monitor by the use of a second level of lookup tables, and analog RGB output is produced.

[CMAP RAM Organisation]

FIGURE 10 Organisation of the CMAP RAM (indexed by row).

(NB: there is an error in this section. Figure 8 is not correct. The manual has accidentally used Fig10 instead)

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